1/**
2  ******************************************************************************
3  * @file    stm32l1xx_i2c.h
4  * @author  MCD Application Team
5  * @version V1.0.0RC1
6  * @date    07/02/2010
7  * @brief   This file contains all the functions prototypes for the I2C firmware
8  *          library.
9  ******************************************************************************
10  * @copy
11  *
12  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18  *
19  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
20  */
21
22/* Define to prevent recursive inclusion -------------------------------------*/
23#ifndef __STM32L1xx_I2C_H
24#define __STM32L1xx_I2C_H
25
26#ifdef __cplusplus
27 extern "C" {
28#endif
29
30/* Includes ------------------------------------------------------------------*/
31#include "stm32l1xx.h"
32
33/** @addtogroup STM32L1xx_StdPeriph_Driver
34  * @{
35  */
36
37/** @addtogroup I2C
38  * @{
39  */
40
41/** @defgroup I2C_Exported_Types
42  * @{
43  */
44
45/**
46  * @brief  I2C Init structure definition
47  */
48
49typedef struct
50{
51  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
52                                         This parameter must be set to a value lower than 400kHz */
53
54  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
55                                         This parameter can be a value of @ref I2C_mode */
56
57  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
58                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
59
60  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
61                                         This parameter can be a 7-bit or 10-bit address. */
62
63  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
64                                         This parameter can be a value of @ref I2C_acknowledgement */
65
66  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
67                                         This parameter can be a value of @ref I2C_acknowledged_address */
68}I2C_InitTypeDef;
69
70/**
71  * @}
72  */
73
74
75/** @defgroup I2C_Exported_Constants
76  * @{
77  */
78
79#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
80                                   ((PERIPH) == I2C2))
81/** @defgroup I2C_mode
82  * @{
83  */
84
85#define I2C_Mode_I2C                    ((uint16_t)0x0000)
86#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)
87#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
88#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
89                           ((MODE) == I2C_Mode_SMBusDevice) || \
90                           ((MODE) == I2C_Mode_SMBusHost))
91/**
92  * @}
93  */
94
95/** @defgroup I2C_duty_cycle_in_fast_mode
96  * @{
97  */
98
99#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
100#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
101#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
102                                  ((CYCLE) == I2C_DutyCycle_2))
103/**
104  * @}
105  */
106
107/** @defgroup I2C_acknowledgement
108  * @{
109  */
110
111#define I2C_Ack_Enable                  ((uint16_t)0x0400)
112#define I2C_Ack_Disable                 ((uint16_t)0x0000)
113#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
114                                 ((STATE) == I2C_Ack_Disable))
115/**
116  * @}
117  */
118
119/** @defgroup I2C_transfer_direction
120  * @{
121  */
122
123#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
124#define  I2C_Direction_Receiver         ((uint8_t)0x01)
125#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
126                                     ((DIRECTION) == I2C_Direction_Receiver))
127/**
128  * @}
129  */
130
131/** @defgroup I2C_acknowledged_address
132  * @{
133  */
134
135#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
136#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
137#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
138                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
139/**
140  * @}
141  */
142
143/** @defgroup I2C_registers
144  * @{
145  */
146
147#define I2C_Register_CR1                ((uint8_t)0x00)
148#define I2C_Register_CR2                ((uint8_t)0x04)
149#define I2C_Register_OAR1               ((uint8_t)0x08)
150#define I2C_Register_OAR2               ((uint8_t)0x0C)
151#define I2C_Register_DR                 ((uint8_t)0x10)
152#define I2C_Register_SR1                ((uint8_t)0x14)
153#define I2C_Register_SR2                ((uint8_t)0x18)
154#define I2C_Register_CCR                ((uint8_t)0x1C)
155#define I2C_Register_TRISE              ((uint8_t)0x20)
156#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
157                                   ((REGISTER) == I2C_Register_CR2) || \
158                                   ((REGISTER) == I2C_Register_OAR1) || \
159                                   ((REGISTER) == I2C_Register_OAR2) || \
160                                   ((REGISTER) == I2C_Register_DR) || \
161                                   ((REGISTER) == I2C_Register_SR1) || \
162                                   ((REGISTER) == I2C_Register_SR2) || \
163                                   ((REGISTER) == I2C_Register_CCR) || \
164                                   ((REGISTER) == I2C_Register_TRISE))
165/**
166  * @}
167  */
168
169/** @defgroup I2C_SMBus_alert_pin_level
170  * @{
171  */
172
173#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
174#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
175#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
176                                   ((ALERT) == I2C_SMBusAlert_High))
177/**
178  * @}
179  */
180
181/** @defgroup I2C_PEC_position
182  * @{
183  */
184
185#define I2C_PECPosition_Next            ((uint16_t)0x0800)
186#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
187#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
188                                       ((POSITION) == I2C_PECPosition_Current))
189/**
190  * @}
191  */
192
193/** @defgroup I2C_interrupts_definition
194  * @{
195  */
196
197#define I2C_IT_BUF                      ((uint16_t)0x0400)
198#define I2C_IT_EVT                      ((uint16_t)0x0200)
199#define I2C_IT_ERR                      ((uint16_t)0x0100)
200#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
201/**
202  * @}
203  */
204
205/** @defgroup I2C_interrupts_definition
206  * @{
207  */
208
209#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
210#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
211#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
212#define I2C_IT_OVR                      ((uint32_t)0x01000800)
213#define I2C_IT_AF                       ((uint32_t)0x01000400)
214#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
215#define I2C_IT_BERR                     ((uint32_t)0x01000100)
216#define I2C_IT_TXE                      ((uint32_t)0x06000080)
217#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
218#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
219#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
220#define I2C_IT_BTF                      ((uint32_t)0x02000004)
221#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
222#define I2C_IT_SB                       ((uint32_t)0x02000001)
223
224#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
225
226#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
227                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
228                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
229                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
230                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
231                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
232                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
233/**
234  * @}
235  */
236
237/** @defgroup I2C_flags_definition
238  * @{
239  */
240
241/**
242  * @brief  SR2 register flags
243  */
244
245#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
246#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
247#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
248#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
249#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
250#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
251#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
252
253/**
254  * @brief  SR1 register flags
255  */
256
257#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
258#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
259#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
260#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
261#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
262#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
263#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
264#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
265#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
266#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
267#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
268#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
269#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
270#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
271
272#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
273
274#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
275                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
276                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
277                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
278                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
279                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
280                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
281                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
282                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
283                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
284                               ((FLAG) == I2C_FLAG_SB))
285/**
286  * @}
287  */
288
289/** @defgroup I2C_Events
290  * @{
291  */
292
293/*========================================
294
295                     I2C Master Events (Events grouped in order of communication)
296                                                        ==========================================*/
297/**
298  * @brief  Communication start
299  *
300  * After sending the START condition (I2C_GenerateSTART() function) the master
301  * has to wait for this event. It means that the Start condition has been correctly
302  * released on the I2C bus (the bus is free, no other devices is communicating).
303  *
304  */
305/* --EV5 */
306#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
307
308/**
309  * @brief  Address Acknowledge
310  *
311  * After checking on EV5 (start condition correctly released on the bus), the
312  * master sends the address of the slave(s) with which it will communicate
313  * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
314  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
315  * his address. If an acknowledge is sent on the bus, one of the following events will
316  * be set:
317  *
318  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
319  *     event is set.
320  *
321  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
322  *     is set
323  *
324  *  3) In case of 10-Bit addressing mode, the master (just after generating the START
325  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
326  *  function). Then master should wait on EV9. It means that the 10-bit addressing
327  *  header has been correctly sent on the bus. Then master should send the second part of
328  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
329  *  should wait for event EV6.
330  *
331  */
332
333/* --EV6 */
334#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
335#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
336/* --EV9 */
337#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
338
339/**
340  * @brief Communication events
341  *
342  * If a communication is established (START condition generated and slave address
343  * acknowledged) then the master has to check on one of the following events for
344  * communication procedures:
345  *
346  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
347  *    the data received from the slave (I2C_ReceiveData() function).
348  *
349  * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
350  *    function) then to wait on event EV8 or EV8_2.
351  *    These two events are similar:
352  *     - EV8 means that the data has been written in the data register and is
353  *       being shifted out.
354  *     - EV8_2 means that the data has been physically shifted out and output
355  *       on the bus.
356  *     In most cases, using EV8 is sufficient for the application.
357  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
358  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission
359  *     (before Stop condition generation).
360  *
361  *  @note In case the  user software does not guarantee that this event EV7 is
362  *  managed before the current byte end of transfer, then user may check on EV7
363  *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
364  *  In this case the communication may be slower.
365  *
366  */
367
368/* Master RECEIVER mode -----------------------------*/
369/* --EV7 */
370#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
371
372/* Master TRANSMITTER mode --------------------------*/
373/* --EV8 */
374#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
375/* --EV8_2 */
376#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
377
378
379/*========================================
380
381                     I2C Slave Events (Events grouped in order of communication)
382                                                        ==========================================*/
383
384/**
385  * @brief  Communication start events
386  *
387  * Wait on one of these events at the start of the communication. It means that
388  * the I2C peripheral detected a Start condition on the bus (generated by master
389  * device) followed by the peripheral address. The peripheral generates an ACK
390  * condition on the bus (if the acknowledge feature is enabled through function
391  * I2C_AcknowledgeConfig()) and the events listed above are set :
392  *
393  * 1) In normal case (only one address managed by the slave), when the address
394  *   sent by the master matches the own address of the peripheral (configured by
395  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
396  *   (where XXX could be TRANSMITTER or RECEIVER).
397  *
398  * 2) In case the address sent by the master matches the second address of the
399  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled
400  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
401  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
402  *
403  * 3) In case the address sent by the master is General Call (address 0x00) and
404  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
405  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
406  *
407  */
408
409/* --EV1  (all the events below are variants of EV1) */
410/* 1) Case of One Single Address managed by the slave */
411#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
412#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
413
414/* 2) Case of Dual address managed by the slave */
415#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
416#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
417
418/* 3) Case of General Call enabled for the slave */
419#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
420
421/**
422  * @brief  Communication events
423  *
424  * Wait on one of these events when EV1 has already been checked and:
425  *
426  * - Slave RECEIVER mode:
427  *     - EV2: When the application is expecting a data byte to be received.
428  *     - EV4: When the application is expecting the end of the communication: master
429  *       sends a stop condition and data transmission is stopped.
430  *
431  * - Slave Transmitter mode:
432  *    - EV3: When a byte has been transmitted by the slave and the application is expecting
433  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
434  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
435  *      used when the user software doesn't guarantee the EV3 is managed before the
436  *      current byte end of tranfer.
437  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission
438  *      shall end (before sending the STOP condition). In this case slave has to stop sending
439  *      data bytes and expect a Stop condition on the bus.
440  *
441  *  @note In case the  user software does not guarantee that the event EV2 is
442  *  managed before the current byte end of transfer, then user may check on EV2
443  *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
444  *  In this case the communication may be slower.
445  *
446  */
447
448/* Slave RECEIVER mode --------------------------*/
449/* --EV2 */
450#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
451/* --EV4  */
452#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
453
454/* Slave TRANSMITTER mode -----------------------*/
455/* --EV3 */
456#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
457#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
458/* --EV3_2 */
459#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
460
461/*===========================      End of Events Description           ==========================================*/
462
463#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
464                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
465                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
466                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
467                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
468                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
469                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
470                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
471                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
472                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
473                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
474                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
475                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
476                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
477                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
478                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
479                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
480                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
481                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
482                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
483/**
484  * @}
485  */
486
487/** @defgroup I2C_own_address1
488  * @{
489  */
490
491#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
492/**
493  * @}
494  */
495
496/** @defgroup I2C_clock_speed
497  * @{
498  */
499
500#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
501/**
502  * @}
503  */
504
505/**
506  * @}
507  */
508
509/** @defgroup I2C_Exported_Macros
510  * @{
511  */
512
513/**
514  * @}
515  */
516
517/** @defgroup I2C_Exported_Functions
518  * @{
519  */
520
521void I2C_DeInit(I2C_TypeDef* I2Cx);
522void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
523void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
524void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
525void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
526void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
527void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
528void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
529void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
530void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
531void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
532void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
533void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
534void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
535uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
536void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
537uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
538void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
539void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
540void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
541void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
542void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
543uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
544void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
545void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
546void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
547
548/**
549 * @brief
550 ****************************************************************************************
551 *
552 *                         I2C State Monitoring Functions
553 *
554 ****************************************************************************************
555 * This I2C driver provides three different ways for I2C state monitoring
556 *  depending on the application requirements and constraints:
557 *
558 *
559 * 1) Basic state monitoring:
560 *    Using I2C_CheckEvent() function:
561 *    It compares the status registers (SR1 and SR2) content to a given event
562 *    (can be the combination of one or more flags).
563 *    It returns SUCCESS if the current status includes the given flags
564 *    and returns ERROR if one or more flags are missing in the current status.
565 *    - When to use:
566 *      - This function is suitable for most applications as well as for startup
567 *      activity since the events are fully described in the product reference manual
568 *      (RM0008).
569 *      - It is also suitable for users who need to define their own events.
570 *    - Limitations:
571 *      - If an error occurs (ie. error flags are set besides to the monitored flags),
572 *        the I2C_CheckEvent() function may return SUCCESS despite the communication
573 *        hold or corrupted real state.
574 *        In this case, it is advised to use error interrupts to monitor the error
575 *        events and handle them in the interrupt IRQ handler.
576 *
577 *        @note
578 *        For error management, it is advised to use the following functions:
579 *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
580 *          - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.
581 *            Where x is the peripheral instance (I2C1, I2C2 ...)
582 *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2Cx_ER_IRQHandler() function
583 *            in order to determine which error occured.
584 *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop()
585 *            in order to clear the error flag and source and return to correct
586 *            communication status.
587 *
588 *
589 *  2) Advanced state monitoring:
590 *     Using the function I2C_GetLastEvent() which returns the image of both status
591 *     registers in a single word (uint32_t) (Status Register 2 value is shifted left
592 *     by 16 bits and concatenated to Status Register 1).
593 *     - When to use:
594 *       - This function is suitable for the same applications above but it allows to
595 *         overcome the limitations of I2C_GetFlagStatus() function (see below).
596 *         The returned value could be compared to events already defined in the
597 *         library (stm32f10x_i2c.h) or to custom values defined by user.
598 *       - This function is suitable when multiple flags are monitored at the same time.
599 *       - At the opposite of I2C_CheckEvent() function, this function allows user to
600 *         choose when an event is accepted (when all events flags are set and no
601 *         other flags are set or just when the needed flags are set like
602 *         I2C_CheckEvent() function).
603 *     - Limitations:
604 *       - User may need to define his own events.
605 *       - Same remark concerning the error management is applicable for this
606 *         function if user decides to check only regular communication flags (and
607 *         ignores error flags).
608 *
609 *
610 *  3) Flag-based state monitoring:
611 *     Using the function I2C_GetFlagStatus() which simply returns the status of
612 *     one single flag (ie. I2C_FLAG_RXNE ...).
613 *     - When to use:
614 *        - This function could be used for specific applications or in debug phase.
615 *        - It is suitable when only one flag checking is needed (most I2C events
616 *          are monitored through multiple flags).
617 *     - Limitations:
618 *        - When calling this function, the Status register is accessed. Some flags are
619 *          cleared when the status register is accessed. So checking the status
620 *          of one Flag, may clear other ones.
621 *        - Function may need to be called twice or more in order to monitor one
622 *          single event.
623 *
624 */
625
626/**
627 *
628 *  1) Basic state monitoring
629 *******************************************************************************
630 */
631ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
632/**
633 *
634 *  2) Advanced state monitoring
635 *******************************************************************************
636 */
637uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
638/**
639 *
640 *  3) Flag-based state monitoring
641 *******************************************************************************
642 */
643FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
644/**
645 *
646 *******************************************************************************
647 */
648
649void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
650ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
651void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
652
653#ifdef __cplusplus
654}
655#endif
656
657#endif /*__STM32L1xx_I2C_H */
658/**
659  * @}
660  */
661
662/**
663  * @}
664  */
665
666/**
667  * @}
668  */
669
670/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
671